Efficient MVL Circuit Design with Use of p-CNTFETs and n-CNTFETs
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Efficient MVL Circuit Design with Use of p-CNTFETs and n-CNTFETs

DG-CNTFET simulation. (a) Simulation setup. (b) Simulated n-branch

Design and evaluation of energy-efficient carbon nanotube FET-based quaternary minimum and maximum circuits

A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits - Moaiyeri - 2013 - IET Computers & Digital Techniques - Wiley Online Library

Design and evaluation of energy-efficient carbon nanotube FET-based quaternary minimum and maximum circuits - ScienceDirect

A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits - Moaiyeri - 2013 - IET Computers & Digital Techniques - Wiley Online Library

Design of Area Optimised, Energy Efficient Quaternary Circuits Using CNTFETs

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